1. Field of the Invention
The present invention generally relates to a thermal memory cell/device for reading/writing and erasing information and more particularly, a thermal memory cell/device in which a primary current path for reading/writing/erasing of information does not necessarily involve the storage medium.
2. Description of the Related Art
While conventional memory devices are volatile (i.e., DRAM, SRAM), the demand for a non-volatile (as well as cheap, low power consuming and high density) memory technology has been risen sharply, in particular triggered by the emergence of mobile phones, computers, camcorders etc. Towards this end, several non-volatile memory technologies are being developed such as magnetic tunnel junction RAM (MTJ-RAM), ferroelectric RAM (FERAM) as well as phase-change RAM.
The latter of these technologies is typically based on chalcogenide materials (e.g., GeSbTe alloys), the phase of which can be reversibly programmed between phases (e.g., amorphous and polycrystalline. Specifically, amorphization is accomplished by heating the media above the melting temperature (about 500° C.) and then rapidly cooling with a rate of about 109 K/s. Crystallization is achieved by moderate heating of the media below the melting temperature but above the glass temperature (about 300° C.). The amorphous and crystalline phases exhibit very different physical properties, by which reading of the stored information can be accomplished. For example, the amorphous state has higher electrical resistivity and lower optical reflectivity than the crystalline state.
Such phase-change memory devices have been proposed and some of the concepts have been demonstrated (e.g., see U.S. Publication No. US20020039306A1, U.S. Pat. No. 3,271,591, U.S. Pat. No. 6,314,014, U.S. Pat. No. 6,087,674, U.S. Pat. No. 5,825,046, U.S. Pat. No. 5,714,768, U.S. Pat. No. 5,166,758, U.S. Pat. No. 4,924,436, U.S. Pat. No. 4,876,667, U.S. Pat. No. 5,296,716, and U.S. Pat. No. 6,314,014).
However, a careful look at the prior art reveals that all of these inventions utilize the electrical resistance change of the two phases for reading the state of the cell. Consequently, in all of these assemblies, the primary current path for reading/writing/erasing is realized directly through the phase-change media.
Although, due to the large difference in electrical resistivity between the amorphous and crystalline state (about a factor of 100) the read dynamic range is substantial, this approach is accompanied with several problems, which are discussed in more detail below.
Specifically, phase-change media (i.e., Ge2Sb2Te5) typically exhibit fairly large electrical resistivities, roughly on the order of about 10−1 Ωm and about 10−3 Ωm for the amorphous and (poly)crystalline phase, respectively. For example, for a 180 nm memory cell, which has been recently demonstrated (e.g., see M. Gill et al, “Ovonics Unified Memory: A high performance nonvolatile memory technology for stand alone memory and embedded applications” 2002 IEEE International Solid—State Circuits Conference, page 202), the electrical resistance of the amorphous phase is about 85 kΩ and about 2 kΩ for the amorphous and crystalline phase, respectively.
Clearly, such large electrical resistances can cause major problems if they are part of the write/erase circuit. For example, in order to switch the amorphous phase “back” to the crystalline phase, a substantial voltage has to be applied in order to dissipate enough power for sufficient heating. Although Poole-Frenkel conduction through the phase-change media lowers the device impedance at bias fields of larger than 3×105 V/cm, the high temperatures in combination with large electric fields may easily irreversibly degrade (e.g., by breakdown, which is strongly temperature dependent) the phase-change material, and therefore compromise the device performance.
In addition, as a further complication, the resistance of the phase-change media above the glass temperature is very low, which makes the controlling of the write/erase process very difficult.